With the increasing down-scaling of integrated circuits, there exist increasingly demanding requirements for reducing the sheet resistance of source and drain regions of metal-oxide-semiconductor (MOS) devices, and particularly the sheet resistance of source and drain extension regions. Reduced sheet resistances in the source and drain extension regions may help increase carrier mobility, hence resulting in increased drive currents.
To reduce the sheet resistance of source and drain extension regions, the junction depth of the source and drain extension regions needs to be reduced. In addition, the activation rate of the source and drain extension regions needs to be increased. These can be achieved by performing pre-amorphized implantation (PAI), in which a portion of a silicon substrate is amorphized before the source and drain regions are formed. The PAI has two functions. First, vacancies are created in the semiconductor substrate, so that the subsequently implanted p-type or n-type impurities may occupy the vacancies more easily. Accordingly, the activation rate may be improved. Second, in the amorphized substrate, atoms are arranged randomly, and hence the subsequently implanted p-type or n-type impurities cannot channel through the spaces between the periodically located atoms to reach a great depth. The PAI, however, also incurs problems. For example, after the activation, residue defects may still exist and will cause an increase in leakage currents. Such leakage currents prevent further improvement of device performance.